x86 or Intel 80x86 is the generic name of an architecture of microprocessors first developed and manufactured by Intel.


x86 CPUss are also manufactured at various stages by AMD, Cyrix, NEC, IDT, Transmeta (that uses it in PDAs too, see Crusoe) (arguably) and sundry other makers at various stages in its nearly 25-year history.

In addition to basic architecture itself, these names are also used to describe a family of particular microprocessors manufactured by Intel, including the Intel 8086, Intel 80186, Intel 80286, Intel 80386, Intel 80486, Pentium, Pentium Pro, Pentium II, Pentium III and Pentium 4. For marketing reasons, Intel refers to x86 processors as IA-32 while most of its competitors calls them x86.

Intel's IA-64 architecture used in its Itanium processors is technically backward compatible with x86 processors, but its default 64-bit mode of operation bares no resemblance to the x86 architecture. AMD's AMD64 used in its Opteron and Athlon 64 processors is a more natural extension of the 32-bit x86 instruction set and is also backward-compatible with x86.


The x86 architecture first appeared inside the Intel 8086 CPU in 1978 as a follow on to the 8008 processor (which itself followed the 4004). It was adopted (in the simpler 8088 version) three years later as the standard CPU of the IBM PC. The PC's enormous success during the last 20 years has guaranteed that the x86 architecture that became the most popular CPU architecture ever. See also Intel.


It can be generalized that the x86 architecture is CISC with variable instruction length. Word sized memory access are allowed to unaligned memory addresses. Words are stored in the little-endian order. Backwards compatibility was a driving force behind the development of the x86 architecture, that caused numerous sub-optimal and otherwise unjustifiable design decisions in the early architectures. Modern x86 processors translate the x86 instruction set to more RISC-like micro-instructions upon which modern micro-architectural techniques can be applied.

Note that the names for instructions and registers (mnemonics) that appear in this brief review are the ones specified in Intel documentation and used by some of the assemblers. An instruction that is specified in TASM syntax by mov al, 30h is equivalent to AT&T-syntax movb $0x30, %al, and both translate to the two bytes of machine code B0 30 (hexadecimal). You can see that there is no trace left in this code of either "mov" or "al", which are the original Intel mnemonics. If we wanted, we could write an assembler that would produce the same machine code from the command "move immediate byte hexadecimally encoded 30 into low half of the first register". However, the convention is to stick to Intel's original mnemonics.

The x86 assembly language is discussed in more detail in the x86 assembly language article.

Real mode

Intel 8086 and 8088 had 14 16-bit registers. Four of them (AX, BX, CX, DX) were general purpose (although each had also an additional purpose; for example only CX can be used as a counter with the loop instruction). Each could be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). In addition to them, there are 4 segment registers (CS, DS, SS and ES). They are used to form a memory address. There are 2 pointer registers (SP which points to the bottom of the stack, and BP which can be used to point at some other place in the stack or the memory). There are two index registers (SI and DI) which can be used to point inside an array. Finally, there are the flag register (containing flags such as carry, overflow, zero and so on), and the instruction pointer (IP) which points at the current instruction. Both can't be changed directly.

In real mode, memory access is segmented. This is done by shifting the segment address left by 4 bits and adding an offset in order to receive a final 20-bit address. Thus the total address space in real mode is 220 bits, or 1 MB, quite an impressive figure for 1978. There are two addressing modes: near and far. In far mode, both the segment and the offset are specified. In near mode, only the offset is specified, and the segment is taken from the appropriate register. For data the register is DS, for code is CS, and for stack it is SS. For example, if DS is A000h and SI is 5677h, DS:SI will point at the absolute address DS × 16 + SI = A5677h.

In this scheme, two different segment/offset pairs can point at a single absolute location. Thus, if DS is A111h and SI is 4567h, DS:SI will point at the same A5677h as above. In addition to duplicacy, this scheme also makes it impossible to have more than 4 segments at once. Moreover, CS, DS and SS are vital for the correct functioning of the program, so that only ES can be used to point somewhere else. This scheme, which was intended as a compatibility measure with the Intel 8085 has caused no end of grief to programmers.

In addition to the above-said, the 8086 also had 64K of 8-bit (or alternatively 32K of 16-bit) I/O space, and support for up to 256 interrupts. A 64K (one segment) stack in memory is supported by hardware. Only words (2 bytes) can be pushed to the stack. The stack grows downwards, its bottom being pointed by SS:SP. There are 256 interrupts, which can be created by both the hardware and the software. The interrupts can cascade, using the stack to store the return address.

Protected and Enhanced Modes

The Intel 80286 could support 8086 Real Mode 16-bit software without any changes, however it also supported another mode of work called the Protected Mode, which expanded addressable memory to 16MB. This was done by using the segment registers only for storing an index to a segment table. The segment table provided a 24-bit base address, which could then be added to the desired offset to create an absolute address. In addition, each segment could be given one of four privilege levels (called the rings). Overall, the introductions were an improvements; however they were not used widely per se because using Protected Mode made software incompatible with the Real Mode of 8086.

The Intel 80386 introduced, perhaps, the greatest leap so far in the x86 architecture. It was 32-bit - all the registers, instructions, I/O space and memory. To work with the latter, it used Enhanced Mode, a 32-bit extension of Protected Mode. As it was in the 286, segment registers were used to index inside a segment table that described the division of memory. Unlike the 286, however, inside each segment one could use 32-bit offsets, which allowed every application to access up to 4GB of memory. In addition, Enhanced Mode supported paging, a mechanism which made it possible to use virtual memory.

No new general-purpose registers were added. All 16-bit registers except the segment ones were expanded to 32 bits. Intel represented this by adding "E" to the register mnemonics (thus the expanded AX became EAX, SI became ESI and so on). Since there was a greater number of registers, instructions and operands, the machine code format was expanded as well. In order to provide backwards compatibility, the segments which contain executable code can be marked as containing either 16 or 32 bit instructions. In addition, a special byte prefix can be used to include 32-bit instructions in a 16-bit segment and vice versa.

Paging and segmented memory access were both required in order to support a modern multitasking operating system. Linux, 386BSD, Windows NT and Windows 95 were all initially developed for the 386, because it was the first CPU that made it possible to reliably support the separation of programs' memory space (each into its own address space) and the preemption of them in the case of necessity (using rings). The basic architecture of the 386 (which is also called IA-32) became the basis of all further development in the x86 series, and no significant changes have been made to it since, thus exemplifying the elegance and scalability of the 386's design.

The Intel 80387 math co-processor was integrated into the next CPU in the series, the Intel 80486. The new FPU could be used to make floating point calculations, important for scientific calculation and graphic design.

MMX and beyond

1996 saw the appearance of the MMX (Multimedia Extensions) technology by Intel. While the new technology has been advertised widely and vaguely, its essence is very simple: MMX defined 8 64-bit SIMD registers overlayed onto the FPU stack to the Intel Pentium CPU design. Unfortunately, these instructions were not easily mappable to the code generated by ordinary C compilers, and Microsoft, the dominant compiler vendor, was slow to support them even as intrinsics. MMX also is limited to integer operations. These technical short comings that MMX had little impact in its early existence. Nowadays, MMX is typically used for some 2D video applications.


In 1997 AMD introduced the 3DNow! which were SIMD floating point instruction enchancements to MMX (targetting the same MMX registers). While this did not solve the compiler difficulties, the introduction of this technology coincided with the rise of 3D entertainment applications in the PC space. 3D video game developers, and 3D graphics hardware vendors used 3DNow! to help enhance their performance on AMD's K6 and Athlon line of processors.


In 1999 Intel instroduced the SSE instruction set which added 8 new 128 bit registers (not overlayed with other registers). These instructions were analogous to AMD's 3DNow! in that they primarily added floating point SIMD.


In 2001 Intel instroduced the SSE-2 instruction set which added 1) a complete complement of integers instructions (analogous to MMX) to the original SSE registers and 2) 64-bit SIMD floating point instructions to the original SSE registers. The first addition made MMX nearly obsolete, and the second allowed the instructions to be realistically targeted by conventional compilers.


As of 2002, the x86 architecture has begun to reach some design limits due to the 32-bit word length. This makes it more difficult to handle massive information stores larger than 4 GB such as those found in databases.

Intel and AMD appear to be planning different strategies for the transition to 64-bit architectures. AMD is planning on a generation of chips known as x86-64 (or Hammer) which are compatible with 32-bit x86 chips. Publicly, Intel has stated that it is abandoning the x86 architecture for the radically different Itanium chips. There are rumors that Intel is secretly designing a 64-bit x86 chip to compete with Hammer should AMD begin to capture market share. Intel also has a license for AMD's x86-64 technology, according to their cross-license agreements (Intel and AMD can use each other's technologies freely), [1], [1], [1].


x86 and compatibles have been manufactured by a number of companies, including: This article (or an earlier version of it) contains material from FOLDOC, used with permission.

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